Continued scaling towards 20 nm and 14 nm VLSI CMOS technologies increases marginalities, variability, and changes in manufacturability. Scaling in polysilicon (poly-Si) pitches between devices results in a minimum space where serval implants, stress memorization techniques, salicidation, dual stress liners, and strained contacts have to find space.
Modern integrated circuits use several poly pitches depending on the gate lengths of the devices used. Multiple spacer formations for one device in a technology results in less space for implantation, salicidation, and contact formation, as poly-Si pitch decreases. The spacers need to be removed to make space for a contact isolation layer as well as the contact itself to prevent voids and, therefore, contact shorts from forming. The spacer removal is currently performed after silicide formation with a dry etch that attacks the silicide surface, which increases serial resistance and degrades device performance.
A need therefore exists for methodology enabling fabrication of a low power, high performance semiconductor device with a spacer pullback process that does not attack the source/drain silicide surface and the resulting device.